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Circuit Description
Components for the PLL filter are fitted by default on the board (Figure 6-6 in "Appendix
B – Schematics"). They are calculated to provide a 32 MHz (multiplier factor of 2 and
settling time of 160 μs) Master Clock frequency.
The Voltage Regulator provides 3.3V to the board and will light the red POWER LED
(D11) when operating.
This Voltage Regulator can be turned off by using the APMC shutdown feature when the
JP7 jumper is closed. See Figure 6-8 in "Appendix B – Schematics." A wake-up push
button (S1) is provided to exit this mode. Alternatively, the user can program a RTC
alarm to awake the voltage regulator.
Power can be applied via the 2.1 mm connector to the regulator in either polarity
because of the diode rectifying circuit. Another regulator allows the user to power the
AT91M55800A core with 3.3V or 2V by the mean of the JP8 jumper.
A 3V battery is provided on-board (Figure 6-8 in "Appendix B – Schematics") to power
the RTC and APMC (V DDBU ). It has been provided to ensure the power supply for
approximately 1 year.
4.6
Push Buttons,
LEDs, Reset and
Serial Interface
The IRQ0, TIOA0, PB17 and PB19 switches are debounced and buffered.
A supervisory circuit has been included in the design to detect and, consequently, reset
the board when the 3.3V supply voltage drops below a typical 3.0V threshold. Note that
the threshold can change, depending on the board production series. The supervisory
circuit also provides a debounced reset signal. This device can also generate the reset
signal in case of watchdog timeout as the pin NWDOVF of the AT91M55800A is con-
nected on its input MR.
The assertion of this reset signal will light the red RESET LED D10 and if the CLEAR
RESET push button is pressed the LED D10 will unlight.
Another supervisory circuit separately initializes the microcontroller embedded
JTAG/ICE interface when the 3.3V supply voltage drops below a typical 3.0V threshold.
Note that this voltage can change depending on the board production series. The sepa-
rated reset lines allow the user to reset the board without resetting the JTAG/ICE
interface while debugging. bill
An RC device has been fitted on-board to ensure a correct power-on reset for the bat-
tery power supply modules (V D D B U ) first power up or when V D D B U has been
disconnected. This RC network has been calculated to generate a valid 300 ms mini-
mum pulse width NRSTBU signal.
The schematic, Figure 6-5 in "Appendix B - Schematics" also shows eight general-pur-
pose LEDs connected to Port B PIO pins PB8 to PB15.
Two 9-way D-type connectors P3/4 are provided for serial port connection.
Serial Port A (P3) is used primarily for host PC communication and is a DB9 female con-
nector. TXD and RXD are swapped so that a straight through cable can be used. CTS
and RTS are connected together as are DCD, DSR and DTR.
Serial Port B (P4) is a DB9 male connector with TXD and RXD obeying the standard
RS-232 pin-out. Apart from TXD, RXD and Ground, the other pins are not connected.
A MAX3223 device U10 and associated bulk storage capacitors provide RS-232 level
conversion.
AT91EB55 Evaluation Board User Guide
4-3
1709C–ATARM–28-Apr-05
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